Huawei unveils the semiconductor "Tao's Law," replacing geometric dimensions with the time dimension; Q3 Kirin chips fully adopt logic folding

At the 2026 International Symposium on Circuits and Systems, Huawei's President of the Semiconductor Business Unit He Tingbo officially unveiled "Tao (τ) Law," proposing to replace geometric scaling with time scaling and continuously compress signal propagation delay through logic folding technology, becoming the first new industrial development principle independently proposed by China in the semiconductor field. Based on this law, Huawei has successfully designed and mass-produced 381 chips over the past six years; by 2031, the transistor density of high-end chips is expected to reach a level equivalent to the 1.4nm process node. (Background: The White House and Anthropic reach an agreement; the NSA will fully integrate Claude AI) (Context: DeepSeek V4-Pro announces permanent price cuts: API output costs less than NT$30 per million tokens) Huawei's Director and President of the Semiconductor Business Unit, He Tingbo, delivered a keynote speech titled "Exploration and Practice of New Semiconductor Pathways" at the 2026 International Symposium on Circuits and Systems (ISCAS 2026) held in Shanghai on the 25th, formally proposing "Tao (τ) Law." This marks the first time China has independently proposed a new principle to guide industrial development in the global semiconductor field, signaling a shift in China's chip technology pathway from chasing geometric scaling to systematic delay compression as a brand-new direction. According to Jinse Finance citing People's Daily, the core concept of "Tao's Law" is to replace the "geometric scaling" that the semiconductor industry has followed for decades with "time scaling," aiming to systematically reduce the time constant (Tao τ), and through innovative technologies such as logic folding to continuously compress signal propagation delay, thereby continuously increasing transistor density and achieving the sustainable evolution of semiconductors and electronic systems. He Tingbo pointed out in the speech that based on this new principle, Huawei has successfully designed and mass-produced 381 chips over the past six years, covering multiple fields from terminal devices to infrastructure. This set of figures not only demonstrates Huawei's resilience in maintaining its in-house chip development capabilities under U.S. sanctions pressure but also reflects that "Tao's Law" has received preliminary validation in actual product iterations. These 381 chips cover Huawei's HiSilicon product line, including the Ascend AI accelerator chips, Kunpeng server processors, and the Kirin mobile chip series. Against the backdrop of continued tightening of U.S. export controls, Huawei has gradually established a non-U.S. chip design and production chain, and "Tao's Law" serves as the technical and theoretical foundation of this strategy. He Tingbo also previewed that this autumn Huawei will release a new generation of Kirin mobile chips, fully adopting logic folding technology to significantly enhance related performance. Logic folding technology is one of the important practical means of "Tao's Law"; by reorganizing the internal logic unit layout and interconnect structure of the chip, it achieves optimization of performance and power consumption without relying on advanced process scaling. It is worth noting that this means the new Kirin chips may no longer rely on the most advanced nanometer-level processes (such as 3nm or below), but instead compensate for process limitations through chip architecture innovation. This carries profound significance for the global semiconductor industry landscape—if logic folding technology can be validated in mass production, it will open up a new technical pathway for chip designers constrained by export controls on equipment such as EUV lithography machines. "Tao's Law" constructs a multi-level collaborative optimization system spanning devices, circuits, chips, and system levels. Unlike traditional Moore's Law, which solely pursues the shrinking of transistor linewidth, "Tao's Law" starts from the perspective of system-level time constants and seeks cross-level delay optimization. He Tingbo predicts that by 2031, the transistor density of high-end chips based on this law will reach a level equivalent to the 1.4nm process node. This indicates Huawei's long-term confidence in this technological pathway and sets clear technical milestones for chip R&D over the next five years. The character "Tao" is taken directly from He Tingbo's name, while also implying the meaning of strategy and planning in the phrase "wentao wulüe" (civil and military strategy). The Greek letter τ (tau) is commonly used in physics to represent the time constant, echoing the law's core proposition of delay compression. This naming approach parallels Moore's Law being named after founder Gordon Moore, highlighting the intention of Huawei and even the Chinese semiconductor industry to establish autonomous technological discourse power. Amid the ongoing restructuring of the global chip supply chain and continued U.S.-China tech competition, the proposal of "Tao's Law" is not only a technological declaration but also carries symbolic significance for industrial policy and national strategy.